Chip#1 (Tapeout Date: May 2006)

Designs: UI2C (Ying Su), ADC (Yi Tang), QVCO (Shailesh Rai), Charge Pump (Jeremy Holleman).

UI2C: Unique chip identification circuit (ISSCC 2007, JSSC 2008): A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 130nm CMOS process.

Chip#2 (Tapeout Date: October 2006)

Designs: Amplifier (Jeremy Holleman).

This chip, fabricated in a 0.5um BiCMOS process courtesy of National Semiconductor, contained a single-ended open-loop amplifier intended for neural recording. It achieved the best Noise Efficiency Factor (NEF) of any published bio-signal amplifier, demonstrating that a penalty in deterministic error sources, specifically linearity, supply rejection, and gain accuracy, can be accepted in exchange for dramatically improved noise performance for a fixed current budge. The amplifier was published at EMBC, 2007.

Chip#3 (Tapeout Date: Febraury 2007)

Designs: UI2C (Ying Su), ADC (Yi Tang), QVCO (Shailesh Rai), Spike Sorter (Jeremy Holleman), Oscillator (Steve Zafonte), ADC (Apurva Mishra).

ADC: The neural Analog-to-Digital Converter (ADC) was designed to resolve neural spike peaks and troughs to 8 bits at a sample frequency of 10 to 100 kilo-samples per second. It uses a successive approximation (SAR) architecture and a zero-static-power comparator to minimize power consumption. UI2C: Unique chip identification circuit V2: A modified version of UI2C circuit. Several ID blocks are scattered in several locations of the chips in different orientations. This is designed for ID bits vs. special dependency study.

58 GHz Oscillator: This oscillator combined the copitts topology with distributed microwave techniques to generate transformer coupling. This allowed better phase noise at lower power consumption.

Chip#4 (Tapeout Date: July 2007)

Designs: Spike Sorter (Jeremy Holleman), Oscillator (Ryan Ricchiuti), Divider (Julie Hu).

Oscillator: Low frequency timer for remote sensing applications. Gate leakage is employed to create a very large RC product for a simple, low power relaxation oscillator.

Divider: The bottom portion with GSG probing pads is a ring oscilllator based injection locking divider. It achieves divide-by-5 by consuming only 3uW of powe at a center frequency of 400MHz. This work is published at RFIC08.

Chip#5 (Tapeout Date: January 2008)

Designs: NSC Amp2 (Jeremy Holleman).

A stand-alone neural amplifier was implemented on this chip, which was fabricated in a 0.5um BiCMOS process, courtesy of National Semiconductor. The design was targeted at applications in which energy could be harvested to power a neural interface. Therefore, the design was fairly conservative in order to minimize risk. The amplifier was built around a two-stage op-amp and included a common-collector output stage in order to adapt to widely varying resistive loads. The amplifier was included in the NeuralWISP, a wirelessly powered spike density meter for neural recording. The NeuralWISP was published at BioCAS 2008.

Chip#6 (Tapeout Date: May 2008)

Design: A 1.5GHZ FBAR/CMOS Frequency Reference. (Shailesh Rai, Ying Su, Richard Kim, Aron Dobos).

Chip#7 (Tapeout Date: May 2008)

Designs: Neural Tag V1 (Jeremy Holleman, Jagdish Pandey, Shailesh Rai, Fan Zhang).

AFE: An analog front-end with gain variable from 42-78 dB, including a new complementary fully-differential low-noise amplifier with Noise Efficiency Factor(NEF) of 2.48, followed by a variable-gain amplifier with gain of 2-78dB.

Transmitter: Contains ultra low power transmitter for MICS band. A novel frequency multiplying architecture allows the transmitter to operate at 100kbps while consuming only 400uW of power.

Chip#8 (Tapeout Date: May 2008)

Designs: PLL (Julie Hu), Boost Converter (Eric Carlson), Oscillator (Will Biederman, Steve Zafonte).

PLL: The right portion of the chip reside two PLLs that are identical except that one uses FBAR resonator and another LC tank. This work exploits alternative low power, low phase noise frequency synthesizer solutions. The result is published at RFIC09.

5.5 GHz Oscillator: This oscillator used complementary class-C oscillator techniques with a MIMO tuning loop to keep it operating at a predictable, optimal point. An auto-transformer is used as the designs inductive element. This allows Class-C gm-boosting which reduces power consumption and improves phase noise.

Chip#9 (Tapeout Date: May 2008)

Designs: Accelerometer (Yu-Te Liao, Will Biederman), Frequency Multiplier (Jagdish Pandey).

FM: Contains a differential low power frequency multiplier based on FBAR resonator. It operates at 2GHz and performs 5X frequency multiplication.

Chip#10 (Tapeout Date: September 2008)

Designs: LNA (Jianlei Shi, Steve Zafonte), Oscillator (Shailesh Rai).

Wide tuning LNA: this LNA is designed around a new type of gm-boosting technique which allows for easily switching of inductor turns. The frequency tuning range of the resulting high performance, narrow-band LNA is 300% - extending the capabilities of software defined and cognitive radio.

Chip#11 (Tapeout Date: September 2008)

Designs: Eyechip V1 (Yu-Te Liao, Jagdish Pandey).

Contains RF power harvesting and power management circuit for extreme biotelemetry applications.

Chip#12 (Tapeout Date: November 2008)

Designs: WISP (Dan Yeager, Azin Zarasvand, Fan Zhang), Neural Tag V2 (Jeremy Holleman, Jagdish Pandey, Shailesh Rai, Fan Zhang).

LNA: A chopper-stabilized low-noise amplifier with a bandwidth of 300Hz, for ECoG/EEG applications. It is also interfaced with the rest of Neurowisp.

SoC-WISP is a UHF RFID tag with the capability of transferring sensor data. This chip includes following blocks:

Rectifier
Demodulator
Bias Generator
0.6 V, 1.2 V, and 1.8 V Voltage Regulators
Voltage Sensor
Oscillator
Digital Section for implementing Gen2 protocol and communicating with sensors.

Chip#13 (Tapeout Date: November 2008)

Designs: Eyechip V2 (Yu-Te Liao, Jagdish Pandey).

Adds communication functionality to the iChip1.0 platform.