Chip Gallery

Chip#42 (Tapeout Date: May 2015; 65nm CMOS)


A 350uW 2GHz FBAR Transformer coupled colpitts oscillator with close-in phase noise reduction, Published in CICC 2017. (Jabeom Koo)

Chip#41 (Tapeout Date: June 2014; 65nm CMOS)


A +/-3ppm 1.1mW FBAR frequency reference with 750MHz output and 750mV supply, Published in ISSCC 2015. (Kannan Sankaragomathi, Jabeom Koo)

Chip#40 (Tapeout Date: June 2014; 65nm CMOS)


A 0.8mm³ +/-0.68psi Single-chip wireless pressure sensor for TPMS applications, Published in ISSCC 2015. (Manohar Nagaraju)

Chip#39 (Tapeout Date: June 2014; 65nm CMOS)


A 400uW differential FBAR sensor Interface IC with digital readout, Published in FCS 2015. (Manohar Nagaraju)

Chip#38 (Tapeout Date: June 2013; 65nm CMOS)


A 10uA On-chip Electrochemical Impedance Spectroscopy system for Wearables/Implantables, Published in ASSCC 2014. (Jingren Gu)

Chip#37 (Tapeout Date: June 2013; 65nm CMOS)


A 27uW subcutaneous single chip wireless biosensing platform with optical power and data transfer, Published in CICC 2014. (Kannan Sankaragomathi, Luis Perez)

Chip#36 (Tapeout Date: June 2013; 65nm CMOS)


A 1.8mW PLL-Free Channelized 2.4GHz ZigBee Receiver Utilizing Fixed-LO Temperature-Compensated FBAR Resonator, Published in ISSCC 2014. (Keping Wang, Jabeom Koo)

Chip#35 (Tapeout Date: Nov 2012; 130nm CMOS)


A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoring, Published in VLSI 2014. (Tim Morrison, Jason Silver)

Chip#34 (Tapeout Date: May 2012; 130nm CMOS)


Low phase noise, Colpitt’s Oscillator using AlN Contour mode resonator. Published in CICC 2013 (Jabeom Koo)

Chip#33 (Tapeout Date: May 2012; 65nm CMOS)


A 2.4 GHz receiver that operates from a supply voltage of only 300 mV, the lowest report to date. It allows direct powering from various energy harvesting sources. Published in ISSCC 2013 (Fan Zhang, Jabeom Koo)

Chip#32 (Tapeout Date: Nov 2011; 130nm CMOS)


A 0.5 cm³ Four-Channel 1.1 mW Wireless Biosignal Interface With 20 m Range. Published in Transactions on Biomedical Circuits and Systems, 2013 (Tim Morrison, Manohar Nagaraju).

Chip#31 (Tapeout Date: Nov 2011; 130nm CMOS)


Low phase noise, Wideband Coupled FBAR based oscillator with 3.75% tuning range. Digital Cap Bank Tuning. Published in Ultrasonics Symposium, 2012 (Manohar Nagaraju, Kannan Sankaragomathi).

Chip#30 (Tapeout Date: May 2011; 130nm CMOS)


Low phase noise, Wideband Coupled FBAR oscillator with 3.3% tuning range, Analog varactor tuning. Results published in Ultrasonics Symposium, 2012(Manohar Nagaraju, Kannan Sankaragomathi)

Chip#29 (Tapeout Date: Jan 2011; hp25 BJT process)


Low phase noise/jitter 2.6 GHz FBAR differential chip-scale oscillator. Pad metallization, lid with HP25 VCO circuit and ZDR base wafer. Published in FCS 2012 (Fan Zhang).

Chip#28 (Tapeout Date: Jan 2011; 180nm CMOS)


Low Power 2.0 GHz FBAR Oscillator (Andrew Nelson): Lowest power FBAR oscillator reported to date (22uW). Published in RFIC 2011.

Chip#27 (Tapeout Date: Nov 2010; 130nm CMOS)


Batteryless 19uW MICS/ISM-band Energy Harvesting Body Area Sensor Node SoC. (Fan Zhang, Jason Silver, Manohar Nagaraju, Jagdish Pandey, etc. and the University of Virgina team.) Published in ISSCC 2012.

Chip#26 (Tapeout Date: Nov 2010; 130nm CMOS)


Eyechip V5 (Yu-Te Liao): Readout IC for wireless glucose sensing on a contact lens

Chip#25 (Tapeout Date: Aug 2010; 130nm CMOS)


ECoG aquisition exploiting biosignal properties for power reduction (Apurva Mishra)Description forthcoming (Jianlei Shi)

Chip#24 (Tapeout Date: May 2010, 65nm CMOS)


Low power dividerless all-digital FBAR based PLL (Julie Hu).

Chip#23 (Tapeout Date: May 2010)


Ultra-low power MICS band transceiver (Jagdish Pandey) (ISSCC 2011)Low-power FBAR based Wake-up receiver (Jianlei Shi)RF Injection-locked divider used in biomedical applications (Fan Zhang). (RFIC 2011)

Chip#22 (Tapeout Date: March 2010)


2-axis Wireless Accelerometer (Yu-Te Liao, Jianlei Shi): This chip includes 2-axis readout circuits and wireless transmitter with the high speed GFSK modulation using an open loop divider and a configurable frequency demodulation scheme.DC-DC converter for energy harvesting (Yi-Chun Shih)

Chip#21 (Tapeout Date: May 2010)


Temperature sensor and readout circuitry for an active contact lens (Yu-Te Liao)

Chip#20 (Tapeout Date: Nov 2009)


Ultra-low power MICS band receiver (Jagdish Pandey)Low-power FBAR based Wake-up receiver (Jianlei Shi)Wireless intraocular pressure/temperature sensor (Yi-Chun Shih)

Chip#19 (Tapeout Date: November 2009)


Wide-band digitally-controlled FBAR oscillator (Julie Hu): A Pierce FBAR oscillator that is digitally controlled using an 8-bit switched-capacitor array. Optimized for a wide tuning range to operate over wide PVT variations when used as an RF frequency reference.

Chip#18 (Tapeout Date: July 2009; 130nm CMOS)


Accelerometer v2.0 (Yu-Te Liao, Jianlei Shi): 2-axis wireless accelerometer: This chip includes two axis sensing bondwire oscillators and a 2.4GHz bluetooth compatible transmitter to wirelessly transmit data

ECoG/EEG Acquisition Frontend (Fan Zhang, Apurva Mishra): Analog processing for information extraction and low-power raw-data acquisition modes

Chip#17 (Tapeout Date: July 2009)


Designs: Quartz-less 315-450MHz TX with FBAR/CMOS frequency reference (Shailesh Rai, Ying Su, Ryan)
Sub-100uW MICS/ISM band TX (Jagdish Pandey)

Series FBAR oscillator (Julie Hu): The circuit is designed to oscillate at the series resonance of an FBAR to utilize the better temperature stability. Used a cross-coupled differential pair with source degeneration given by an FBAR tank which has a boosted series resonant impedance. The result was published in RFIC 2010.

Chip#16 (Tapeout Date: July 2009)


Designs: Quartz-less 315-450MHz TX with FBAR/CMOS frequency reference (Shailesh Rai, Ying Su, Ryan)
24GHz low power receiver front-end (Jagdish Pandey).

Series FBAR oscillator (Julie Hu): The circuit is designed to oscillate at the series resonance of an FBAR. Used a cross-coupled differential pair with source degeneration given by an FBAR tank which has a boosted series resonant impedance. The result was published in RFIC 2010.

Chip#15 (Tapeout Date: July 2009)


Designs: 24GHz Phase-Array Transceiver (Jagdish Pandey)

Wide-band FBAR all digital PLL (ADPLL) at lower left corner (Julie Hu)

2×1 low-power 24GHz phased array receiver for sensing application (Jagdish Pandey).

Wide-band FBAR ADPLL: Realize a wide tuning range, low jitter, low power RF frequency reference through PLL techniques. It consists of a wide tuning digitally-controlled FBAR-based oscillator, a configurable digital loop filter, a coarse/fine digital phase detector, and an integer-N divider.

Chip#14 (Tapeout Date: July 2009)


Designs: Eyechip V3 (Jagdish Pandey, Yu-Te Liao).

Adds temperature sensing functionality and fully-integrated ULP supply regulator.

Chip#13 (Tapeout Date: November 2008)


Designs: Eyechip V2 (Jagdish Pandey, Yu-Te Liao).

Adds communication functionality to the iChip1.0 platform.

Chip#12 (Tapeout Date: November 2008)


Designs: WISP (Dan Yeager, Azin Zarasvand, Fan Zhang), Neural Tag V2 (Jeremy Holleman, Jagdish Pandey, Shailesh Rai, Fan Zhang).

LNA: A chopper-stabilized low-noise amplifier with a bandwidth of 300Hz, for ECoG/EEG applications. It is also interfaced with the rest of Neurowisp.

SoC-WISP is a UHF RFID tag with the capability of transferring sensor data. This chip includes following blocks:

  1. Rectifier
  2. Demodulator
  3. Bias Generator
  4. 0.6 V, 1.2 V, and 1.8 V Voltage Regulators
  5. Voltage Sensor
  6. Oscillator
  7. Digital Section for implementing Gen2 protocol and communicating with sensors.

Chip#11 (Tapeout Date: September 2008)


Designs: Eyechip V1 (Jagdish Pandey, Yu-Te Liao).

Contains RF power harvesting and power management circuit for extreme biotelemetry applications.

Chip#10 (Tapeout Date: September 2008)


Designs: LNA (Jianlei Shi, Steve Zafonte), Oscillator (Shailesh Rai).

Wide tuning LNA: this LNA is designed around a new type of gm-boosting technique which allows for easily switching of inductor turns. The frequency tuning range of the resulting high performance, narrow-band LNA is 300% – extending the capabilities of software defined and cognitive radio.

Chip#9 (Tapeout Date: May 2008)


Designs: Accelerometer (Yu-Te Liao, Will Biederman), Frequency Multiplier (Jagdish Pandey).

FM: Contains a differential low power frequency multiplier based on FBAR resonator. It operates at 2GHz and performs 5X frequency multiplication.

Accel_V1: This prototype accelerometer demonstrates bondwire inertial sensing mechanism and consists of an FM demodulator to read out the frequency deviations which is induced by acceleration.

Chip#8 (Tapeout Date: May 2008)


Designs: PLL (Julie Hu), Boost Converter (Eric Carlson), Oscillator (Will Biederman, Steve Zafonte).

PLL: The right portion of the chip reside two PLLs that are identical except that one uses FBAR resonator and another LC tank. This work exploits alternative low power, low phase noise frequency synthesizer solutions. The result is published at RFIC09.

5.5 GHz Oscillator: This oscillator used complementary class-C oscillator techniques with a MIMO tuning loop to keep it operating at a predictable, optimal point. An auto-transformer is used as the designs inductive element. This allows Class-C gm-boosting which reduces power consumption and improves phase noise.

Chip#7 (Tapeout Date: May 2008)


Designs: Neural Tag V1 (Jeremy Holleman, Jagdish Pandey, Shailesh Rai, Fan Zhang).

AFE: An analog front-end with gain variable from 42-78 dB, including a new complementary fully-differential low-noise amplifier with Noise Efficiency Factor(NEF) of 2.48, followed by a variable-gain amplifier with gain of 2-78dB.

Transmitter: Contains ultra low power transmitter for MICS band. A novel frequency multiplying architecture allows the transmitter to operate at 100kbps while consuming only 400uW of power.

Chip#6 (Tapeout Date: May 2008)


Design: A 1.5GHZ FBAR/CMOS Frequency Reference. (Shailesh Rai, Ying Su, Richard Kim, Aron Dobos).

Chip#5 (Tapeout Date: January 2008)


Designs: NSC Amp2 (Jeremy Holleman).

A stand-alone neural amplifier was implemented on this chip, which was fabricated in a 0.5um BiCMOS process, courtesy of National Semiconductor. The design was targeted at applications in which energy could be harvested to power a neural interface. Therefore, the design was fairly conservative in order to minimize risk. The amplifier was built around a two-stage op-amp and included a common-collector output stage in order to adapt to widely varying resistive loads. The amplifier was included in the NeuralWISP, a wirelessly powered spike density meter for neural recording. The NeuralWISP was published at BioCAS 2008.

Chip#4 (Tapeout Date: July 2007)


Designs: Spike Sorter (Jeremy Holleman), Oscillator (Ryan Ricchiuti), Divider (Julie Hu).

Oscillator: Low frequency timer for remote sensing applications. Gate leakage is employed to create a very large RC product for a simple, low power relaxation oscillator.

Divider: The bottom portion with GSG probing pads is a ring oscilllator based injection locking divider. It achieves divide-by-5 by consuming only 3uW of powe at a center frequency of 400MHz. This work is published at RFIC08.

Chip#3 (Tapeout Date: Febraury 2007)


Designs: UI2C (Ying Su), ADC (Yi Tang), QVCO (Shailesh Rai), Spike Sorter (Jeremy Holleman), Oscillator (Steve Zafonte), ADC (Apurva Mishra).

ADC: The neural Analog-to-Digital Converter (ADC) was designed to resolve neural spike peaks and troughs to 8 bits at a sample frequency of 10 to 100 kilo-samples per second. It uses a successive approximation (SAR) architecture and a zero-static-power comparator to minimize power consumption. UI2C: Unique chip identification circuit V2: A modified version of UI2C circuit. Several ID blocks are scattered in several locations of the chips in different orientations. This is designed for ID bits vs. special dependency study.

58 GHz Oscillator: This oscillator combined the copitts topology with distributed microwave techniques to generate transformer coupling. This allowed better phase noise at lower power consumption.

Chip#2 (Tapeout Date: October 2006)


Designs: Amplifier (Jeremy Holleman).

This chip, fabricated in a 0.5um BiCMOS process courtesy of National Semiconductor, contained a single-ended open-loop amplifier intended for neural recording. It achieved the best Noise Efficiency Factor (NEF) of any published bio-signal amplifier, demonstrating that a penalty in deterministic error sources, specifically linearity, supply rejection, and gain accuracy, can be accepted in exchange for dramatically improved noise performance for a fixed current budge. The amplifier was published at EMBC, 2007.

Chip#1 (Tapeout Date: May 2006)


Designs: UI2C (Ying Su), ADC (Yi Tang), QVCO (Shailesh Rai), Charge Pump (Jeremy Holleman).

UI2C: Unique chip identification circuit (ISSCC 2007, JSSC 2008): A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 130nm CMOS process.